(1) Field of the Invention
The present invention relates to a method for producing a semiconductor device and more particularly to a process for forming fuses in an integrated circuit. The present invention can be suitably applied to form polycrystalline silicon fuses in a large-scale integration (LSI) memory.
(2) Description of the Prior Art
The total number of bits of a large capacity LSI memory, such as a 64K-bit dynamic random access memory, has been rapidly increased recently. In order to improve the yield, a redundancy organization is incorporated into the memory. The redundancy organization comprises spare rows and spare columns which are formed near a memory array. If a defective memory element (i.e., a defective bit) is generated, the row and the column forming the defective memory element are replaced with a spare (redundant) row and column. Replacement of the defective memory element is carried out by selectively blowing fuses (i.e., fusible links) which are provided in the memory device. The fuses are made of, e.g., polycrystalline silicon and are blown by an excess electric current or by irradiation with a laser beam.
The polycrystalline silicon fuses are formed around a memory array and in a LSI memory chip. One of the fuses is illustrated in FIGS. 1 and 2. As FIG. 1 shows, the fuse 1 comprises a narrow center portion 2 and wide end portions 3 and 4. The fuse 1 is formed by depositing a polycrystalline silicon layer on an insulating layer 5 of, e.g., silicon dioxide (SiO.sub.2), formed on a semiconductor substrate 6 of, e.g., a silicon single crystalline wafer (FIG. 2) and selectively etching the polycrystalline silicon layer. Then an insulating layer 7, e.g., phosphosilicate glass (PSG), for insulating the polycrystalline silicon layer and a subsequently formed aluminum layer is formed on the fuse 1 and the insulating layer 5 (FIG. 2). Conductors 8 and 9 (FIG. 1) are formed by depositing a conductor layer, e.g., aluminum on the insulating layer 7 and selectively etching the conductor layer by means of a photo-etching method. The conductors 8 ad 9 are conected to the wide end portions 3 and 4, respectively, by way of through holes 10 and 11 formed in the insulating layer 7. A passivation layer 12, e.g., PSG, is formed on the whole surface of the obtained memory devices.
In order to easily and reliably blow the fuse 1, the passivation layer 12 and the insulating layer 7 are selectively etched to form a window 13 by which the narrow center portion 2 is exposed. In this case, since the SiO.sub.2 of the insulating layer 5 is akin to the PSG of the layers 7 and 12, the SiO.sub.2 layer 5 can be etched with an etchant used to etch the PSG layers 7 and 12. Furthermore, usually, the total thickness of the PSG layers 7 and 12 is about 2 .mu.m and the thickness of the SiO.sub.2 layer 5 is about 0.5 .mu.m. Accordingly, during the formation of the window 13 by etching the PSG layers 7 and 12, the SiO.sub.2 layer 5 can also be etched (as is shown in FIG. 2) so that a portion of the semiconductor substrate 6 may be exposed. If the semiconductor substrate 6 is exposed by the window 13, when the fuse 1 is blown, shortcircuiting may occur between the semiconductor substrate 6 and the blown fuse. When the SiO.sub.2 layer 5 is thin, undesirable impurities, such as moisture and ions in the air, may penetrate into the semiconductor substrate 6 through the thin SiO.sub.2 layer 5, with the result that the reliability of the LSI memory is decreased.